High Performance APLL with Multiple Output
- Parameters
- Features
- Description
Part Number | SQ82201QHQ |
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Description | Clock Generator |
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Outputs | 3 differential + 7 Single End |
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Output Type | LVPECL/ LVCMOS |
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Output Freq Range (MHz) | 25/33.33/100/125/156.25 |
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Input Freq (MHz) | 25 |
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Inputs | 2 |
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Input Type | Crystal, LVCMOS |
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Output Banks | 5 |
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Core Voltage (V) | 3.3 |
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Phase Jitter Typ RMS (fs) | 150 |
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Package | QFN6x6-40 |
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- 7 Single-ended LVCMOS Outputs:
- One Single-ended LVCMOS 33.33MHz CPU Clock
- Six Single-ended LVCMOS Outputs from the Reference Clock
- 3 LVPECL Differential Output Pairs, 1 pair 156.25MHz, 2 pairs selectable 100MHz and 125MHz
- Selectable Input Source: External Crystal or external Single-ended Input Source
- 25MHz Crystal Oscillator Reference
- RMS Phase Jitter 0.127ps(Typical)@ 156.25MHz, Reference 25MHz Crystal (12kHz~20MHz)
- Power Supply Noise Rejection PSRR: -90dBc
- 3.3V Power Supply Voltage
- Ambient Operating Temperature: -40°C to 85°C
- Package: QFN6x6-40
The SQ82201 is an analog PLL for Ethernet and processor applications. The SQ82201 will provide <0.15ps RMS phase jitter performance @ 156.25MHz and synthesize output 100MHz, 125MHz, 156.25MHz and a 33.33MHz CPU clock from a single device. Six LVCMOS outputs also serve as additional buffering of the 25MHz crystal reference; 3 differential output support LVPECL format.
Evaluation Board
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Photo of evaluation board
Photo of evaluation board
Photo of evaluation board
Photo of evaluation board
Photo of evaluation board
The EVB_SQ82201QHQ is intended for High Performance APLL with Multiple Output.