High Efficiency High Integration PMIC for SSD System
- Parameters
- Features
- Description
Part Number | SY21572PZS |
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Vin_min (V) | 2.8 |
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Vin_max (V) | 5.5 |
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Channels | 5 Chs Buck+2 CHs LDO |
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Features / Special Function | 3.4MHz I2C, Hardware sleep control; Reset output; Auto PFM/FCCM control; OVP/OCP/SCP/OTP. Enable Output Control |
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Application | SSD |
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Package | CSP3.2x3.2-52 |
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- 2.8V to 5.5V input voltage range
- Channel 1 synchronous buck:
- Low RDS(ON) for internal switches (PFET/NFET): 150/150 mΩ
- 0.9A maximum output current capability.
- Default Output Voltage VOUT1=1.8V
- Channel 2 LDO1:
- 0.3A output current capability.
- Default output voltage VOUT2=1.8V
- Channel 3 synchronous buck:
- Low RDS(ON) for internal switches (PFET/NFET): 45/20 mΩ
- 4.0A maximum output current capability.
- Default output voltage VOUT3=0.9V.
- 0.7V to 1.1V programmable, 10mV step.
- Channel 4 synchronous buck:
- Low RDS(ON) for internal switches (PFET/NFET): 35/45 mΩ
- 4.0A maximum output current capability.
- Default output voltage VOUT4=3.15V
- Channel 5 synchronous buck:
- Low RDS(ON) for internal switches (PFET/NFET): 60/40 mΩ
- 2.0A output current capability.
- Default output voltage VOUT5=1.2V
- Channel 6 LDO2:
- 0.3A output current capability.
- Channel 7 synchronous buck:
- Low RDS(ON) for internal switches (PFET/NFET): 60/40 mΩ
- 2.0A output current capability.
- Reset input/output function
- 2.0MHz switching frequency for Buck converters
- Auto PWM/PFM mode or forced PWM mode controlled by I2C interface
- I2C interface up to 3.4MHz
- Output voltage level of CH3/CH4 controlled by I¬2C interface with DVS function
- Dedicated sleep mode controlled by GPIO1/GPIO2, PMRST
- Reliable Protections:
- Over Voltage Protection (OVP)
- Over Current Protection (OCP)
- Short Circuit Protection (SCP)
- Over Temperature Protection (OTP)
- Compact package: CSP3.2x3.2-52(0.4mm pitch)
The SY21572 is a high efficiency PMIC with 5-channel synchronous buck converters and 2-channel LDOs. It is a single chip total power solution for SSD system.
The output voltage of each channel is controlled by the processor using I2C interface. It therefore supports DVS (Dynamic Voltage Scaling) function for each channel. SY21572 can generate an open-drain reset output for the processor with certain delay time.
The SY21572 operates over a wide input voltage range from 2.8V to 5.5V. It is available in CSP3.2x3.2-52 package.
Evaluation Board
Photo of evaluation board
Photo of evaluation board
Photo of evaluation board
Photo of evaluation board
Photo of evaluation board
Photo of evaluation board
The EVB_ SY21572PZS is intended for evaluating 7-channel PMIC with 5 Step Down Buck Regulators and 2 Low Dropout LDO.